1. Field of the Invention
This invention relates generally to methods, machine readable media and apparatus for protecting intellectual property (“IP”). More specifically, this invention relates to a technique for providing controlled use of IP.
2. Description of Related Art
Electronic design automation (“EDA”) is becoming increasingly complicated and time consuming, due in part to the increasing size and complexity of the devices designed by EDA tools. The design of even the simplest of these devices typically involves generation of a high level architecture and RTL design, logic simulation, logic synthesis, timing simulation, etc. Such devices, referred to as a “logic devices” herein, include general purpose microprocessors and custom logic devices such as programmable logic devices, application specific integrated circuit (ASIC) emulators, application specific standard product (ASSP) emulators and/or ASSP devices that possess special or optional features that can be accessed by an authorized user.
A programmable logic device (“PLD”) is a programmable integrated circuit that allows the user of the circuit, using software control, to program the PLD to perform particular logic functions. A wide variety of these devices are manufactured by Altera Corporation of San Jose, Calif. When an integrated circuit manufacturer supplies a typical programmable logic device, it is not yet capable of performing any specific function. The user, in conjunction with software supplied by the manufacturer or created by the user or an affiliated source, can program the PLD to perform a particular function or functions required by the user's application. One or more of these programmed functions can be found in what is referred to commonly as a “core” within a PLD. These cores provide compartmentalized functional blocks that can be used within a programmed PLD or other logic device. PLDs also are used frequently as application specific integrated circuit (ASIC) emulators and application specific standard product (ASSP) emulators. As will be appreciated by those skilled in the art, the present invention also may be used in connection with a device such as an ASSP having special or optional features hard-wired into the device (where the control circuitry disclosed herein can be used with a key or authorization code to access or enable one or more such special or optional features). Once a logic device such as a PLD is programmed with one or more of such cores, as well as any other logic as needed, the PLD can function in a larger system designed by the user just as though dedicated logic chips were employed.
One improvement in this field is the development of so-called “megafunctions” by companies such as Altera Corporation. Briefly, megafunctions are pre-designed, pre-tested, parameterized cores (or blocks of IP) which, when used, complement and augment existing design methodologies. When implementing complex system architectures, these megafunctions significantly enhance the design process. By using megafunctions, designers can focus more time and energy on improving and differentiating their system-level product, rather than re-designing frequently used functions.
As mentioned above, megafunctions are pre-designed, pre-verified parameterized implementations of system-level functions which reduce the customer's design task to creating the custom logic surrounding such commonly used system-level functions, dramatically shortening the design cycle by leveraging such existing intellectual property (“IP”), which can include proprietary apparatus, structures, techniques and methods applicable to the design field. Typically, an IP owner provides all of the files necessary to design with the megafunctions. Current practice allows designers to instantiate, compile and simulate a function to verify its operation, size and performance; however, programming files and other output files for implementing the design in hardware can be generated only with an authorization code provided when the megafunction is licensed.
A typical design cycle (using, for example, Altera's OpenCore technology) is shown in FIG. 1. A designer creates an initial block diagram 110 and subsequently identifies any megafunctions available for use in the anticipated system 120. The designer then can identify and evaluate one or more specific megafunctions 130 in terms of functionality and the range of parameterization available. After finding the appropriate megafunction(s), the designer installs the megafunction(s) 140, completes the design 145 and, using software, synthesizes and simulates 150 the functionality and performance and estimates the hardware resources in the PLD required to implement the function within the anticipated circuitry and system.
However, software simulations of complex systems that incorporate IP frequently are limited in a number of respects. For example, many hours of software simulation of a circuit used in a voice over technology might translate into only a few seconds of equivalent circuit activity on a hardware platform. As a further example, a system may have an extremely large number of states, all of which the designer may need to test or otherwise evaluate. However, due to the relatively slow speed of some software simulations, only a limited number of states might be testable by such software simulation. Because a hardware platform may run at much higher speeds than software simulations, a designer may need and/or want to test the design on a hardware platform as well. With regard to PLDs, software simulation for several hours (representing a few seconds of PLD hardware operation) might represent appropriate evaluation time for a design. Yet, to thoroughly validate the system which may include one or more cores in such an application, the system (sometimes including several cores) must run in hardware for several minutes to several hours or more, thus making thorough software simulation testing inadequate and/or impractical. Therefore, complex IP (for example, in video applications or voice over IP) should be evaluated and validated on a hardware platform before being purchased.
In such applications, in order to fully validate and complete the system's design, as called for in step 160, the system frequently operates on a hardware prototype platform for a longer period of time than is practical for software simulation. After software simulation and synthesis, the IP owner authorizes the customer 155 (via a license or other authorization means) to generate programming data, such as a programming object file (a “POF” file) or an SRAM object file (a “SOF” file) of the design containing the IP, and to establish the hardware prototype. A hardware prototype platform is substantially identical to the production version of the hardware a designer intends to create. The hardware prototype can be a PLD or other device, or a system or subsystem of the total design to be created. As will be appreciated by those of ordinary skill in the art, the particulars of a hardware prototype are dependent upon the needs and circumstances of the project being undertaken by a designer and will vary widely. In the context of this disclosure, the term “hardware prototype” will mean any hardware platform suitable for evaluating and/or testing the hardware and available software for the system being designed. This hardware prototype also may be referred to herein as the “evaluation version” of a core, design or programmed device. The term “production hardware” means the desired final configuration of any hardware that the designer intends to achieve. Once this hardware prototype validation is completed, the customer can obtain from the IP owner production use authorization (such as a license) 165, after which the IP used can be incorporated into specific devices 170 and be put into production use.
Many IP owners have had to rely on legal contracts and/or other, unverifiable means to limit and control use of their IP on hardware platforms during prototype evaluation (step 160 of FIG. 1) and during production use (step 170 of FIG. 1). Customers have been able to generate a file that could be used both for prototype evaluation as well as in production. Unauthorized use in production deprives the IP owner of compensation for use of its IP and inhibits the owner's control of its property. Attempts at technical measures to prevent unauthorized use of IP also have been only modestly effective. For example, there have been attempts to send an entire prototype “package” (a PLD with the system installed and with its own power supply) to a customer for limited evaluation. Such a pre-packaged system was intended to allow hardware evaluation, without unauthorized production use. However, the delicate nature of these systems and the need for the IP owner to incur significant costs in this method make it unattractive and ineffective.
One other solution to these problems is available using a technique that is the subject of U.S. patent application Ser. No. 09/823,700, entitled METHOD AND APPARATUS FOR PROVIDING A PROTECTED INTELLECTUAL PROPERTY HARDWARE, filed Mar. 30, 2001, and assigned to Altera Corp., which is incorporated herein by reference in its entirety for all purposes. One or more aspects of the embodiments discussed in the above-cited application are incorporated in Altera's OpenCore Plus feature that is described in Application Note 176 from Altera Corporation of San Jose, Calif. In the system discussed in the above-cited application, various techniques provide a means for potential users of PLDs to evaluate proprietary IP in hardware and thus permit improved development of digital systems and devices by designers while protecting the interests of the owners of the intellectual property incorporated in such systems and devices. More specifically, that system provides to an end customer IP hardware which is suitable for prototype evaluation, but unusable for production purposes.
While these techniques, methods, machine readable media and apparatus have provided an effective means for supplementing software evaluation by permitting limited hardware prototype evaluation, there are several shortcomings that arise in its use. First, two different versions of each testable core must be created—a production version designed to run on hardware in normal circumstances, and a evaluation version designed to be time-limited to allow hardware prototype evaluation without production use. Typically, a license is required from the owner of the IP used in each core and the core will be disabled at a set time limit. This technique requires each IP designer to modify each core to create the evaluation version of the core.
The manual process of adding/inserting the disabling logic is time consuming and may lead to errors in the operation of the core in the hardware prototype mode. Moreover, additional verification is needed to insure that the modifications required to limit evaluation time did not break the intended functionality of the core. This technique also requires that, within the “designed logic” (that is, the overall logic designed and constructed by a user, which can contain “protected logic” such as a core incorporating IP and “user logic” which is logic created by the user), each core and each other instantiation of protected logic being evaluated must have its own clock and/or other disabling logic (also referred to as “control logic”) located inside the core. These characteristics can adversely affect the size and performance of the core(s) being evaluated and the hardware environment in general. Any timeout period typically is unalterable, being dictated and fixed by the counter and clock implementations in the modified core containing the control logic. Finally, because different cores may be designed by different designers, or may be designed differently for other reasons, inconsistencies in the evaluation cores' logic and operation can lead to problems. In programs such as the Altera Megafunction Partners Program (AMPP), where third party designers participate in the design and implementation of cores, these drawbacks can present hurdles and/or barriers to such third party participation, thus reducing the amount of IP available for hardware prototyping by users of PLDs and other similar logic devices.
Techniques that permit thorough development and evaluation of digital systems and devices by users, while simplifying the evaluation process, adding flexibility and greater reliability to the process and protecting the proprietary interests of the designers and owners of the intellectual property incorporated in such systems and devices would represent a significant advancement in the art. Moreover, these techniques can be extended to allow an IP owner to limit or prevent unauthorized use of its IP in other settings and contexts (for example, where users employ protected IP in systems and devices shown and used in display, marketing and other non-production contexts).